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Universal (Synchronous/Asynchronous) Receiver Transmitter
The USART offers a very flexible, full-duplex, industrial standard, serial receiver / transmitter.
Including IrDA and modem operations (CTS/RTS).
Features
- Full-, half-duplex communication.
- Fractional baud rate generator.
- 8- and 9 bit word length.
- DMA and interrupt support.
Programming Example
Configuration Registers
CRx
CR1
Configuration register 1
| RE | 0 | Receiver disable (reset state) |
| 1 | Receiver enable | |
| TE | 0 | Transmitter disable (reset state) |
| 1 | Transmitter enable | |
| RXNEIE | 0 | Receiver not empty interrupt disable (reset state) |
| 1 | Receiver not empty interrupt enable | |
| TCIE | 0 | Transmission complete interrupt disable (reset state) |
| 1 | Transmission complete enable | |
| TXEIE | 0 | Transmitter empty interrupt disable (reset state) |
| 1 | Transmitter empty interrupt enable | |
| M | 0 | 8 data bits (reset state) |
| 1 | 9 data bits enable | |
| UE | 0 | USART disable (reset state) |
| 1 | USART enable |
CR2
Configuration register 2
| STOP | 00 | 1 stop bit (reset state) |
| 01 | 0,5 stop bit | |
| 10 | 2 stop bit | |
| 11 | 1,5 stop bit |
BRR
Baud rate register
| Fraction | x | Defines fraction of PCLK divider |
| Mantissa | x | Defines Mantissa of the PCLK divider |
Status Register
SR
| RXNE | 0 | Data is not received |
| 1 | Received data is ready to be read | |
| TC | 0 | Transmission not complete |
| 1 | Transmission complete | |
| TXE | 0 | Data is not transferred to the shift register |
| 1 | Data transferred to the shift register |
Data Register
DR
- Reading from DR register reads from RXDR Buffer.
- Writing to DR register writes to TXDR Buffer.
Legend
