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Reset and Clock Control
Peripheral Configuration Registers
AHB1 Peripherals
AHB2 Peripherals
AHB3 Peripherals
APB1 Peripherals
APB2 Peripherals
Register Description
xxxxENR
| zEN | 0 | Peripheral clock disabled |
| zEN | 1 | Peripheral clock enabled |
xxxxLPENR
| zLPEN | 0 | Peripheral clock disabled during sleep mode |
| zLPEN | 1 | Peripheral clock enabled during sleep mode |
xxxxRSTR
| zLPEN | 0 | Peripheral not reset |
| zLPEN | 1 | Resets peripheral |
Legend
