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Analog Digital Converter
The ADC of the STM32F429ZI has a 12 bit resolution and up to 19 multiplexed channels.
An analog watchdog monitors the input voltage and can take action if necessary.
Features
- Configurable 12-, 10-, 8- or 6 bit resolution.
- Single and continuous conversion modes.
- Programmable conversion time per channel.
- External trigger options.
- Dual / Triple mode with 2 or more ADCs.
- DMA and Interrupt support.
Configuration Registers
ADCCOM→CCR
Common control register
| ADCPRE | 00 | ADCCLK ⇒ fPCLK2 / 2 (reset state) |
| 01 | ADCCLK ⇒ fPCLK2 / 4 | |
| 10 | ADCCLK ⇒ fPCLK2 / 6 | |
| 11 | ADCCLK ⇒ fPCLK2 / 8 |
ADCx→CRx
ADCx→CR1
Configuration register 1
| SCAN | 0 | Scan mode disabled (reset state) |
| 1 | Scan mode enabled | |
| RES | 00 | 12 bit, 15 ADCCLK cycles conversion time (reset state) |
| 01 | 10 bit, 13 ADCCLK cycles conversion time | |
| 10 | 8 bit, 11 ADCCLK cycles conversion time | |
| 11 | 6 bit, 9 ADCCLK cycles conversion time |
ADCx→CR2
Configuration register 2
| ADON | 0 | Disable analog digital converter (reset state) | ||
| 1 | Enable analog digital converter | |||
| CONT | 0 | Single conversion mode (reset state) | ||
| 1 | Continuous conversion mode | |||
| DMA | 0 | DMA mode disabled (reset state) | ||
| 1 | DMA mode enabled | |||
| ALIGN | 0 | Data aligned to the right side (bit 0) (reset state) | ||
| 1 | Data aligned to the left side (bit 15) | |||
| EXTSEL | 0000 | TIM1 CC1 event (reset state) | 1000 | TIM3 TRGO event |
| 0001 | TIM1 CC2 event | 1001 | TIM4 CC4 event | |
| 0010 | TIM1 CC3 event | 1010 | TIM5 CC1 event | |
| 0011 | TIM2 CC2 event | 1011 | TIM5 CC2 event | |
| 0100 | TIM2 CC3 event | 1100 | TIM5 CC3 event | |
| 0101 | TIM2 CC4 event | 1101 | TIM8 CC1 event | |
| 0110 | TIM2 TRGO event | 1110 | TIM8 TRGO event | |
| 0111 | TIM3 CC1 event | 1111 | EXTI line 11 event | |
| EXTEN | 00 | Trigger disabled (reset state) | 10 | Trigger on falling edge |
| 01 | Trigger on rising edge | 11 | Trigger on both edges | |
| SWSTART | 0 | No conversion (reset state) | ||
| 1 | Start conversion of regular channels | |||
ADCx→SMPRx
ADCx→SMPR1
Sample time register 1
ADCx→SMPR2
Sample time register 2
Description
| SMPx | 000 | 3 cycles sampling time (reset state) | 100 | 84 cycles sampling time |
| 001 | 15 cycles sampling time | 101 | 112 cycles sampling time | |
| 010 | 28 cycles sampling time | 110 | 144 cycles sampling time | |
| 011 | 56 cycles sampling time | 111 | 480 cycles sampling time |
ADCx→SQRx
ADCx→SQR1
Sequence register 1
ADCx→SQR2
Sequence register 2
ADCx→SQR3
Sequence register 3
Description
| L* | xxxx | Length of sequence list → nr. of conversions |
| SQy** | xxxxx | Channel nr. of #y conversion |
* Number of Last SQy register used in conversion.
SQ2 ← Channel in this register gets converted after channel in register SQ1.
===== Status Register =====
==== ADCx→SR ====
Status register
Status bits are set by hardware and cleared by software (only possible to write 0).
===== Data Register =====
==== ADCx→DR ====
Data register
* Register is read only
===== Legend =====
===== Programming Example =====
<code c>
#include “reg_stm32f4xx.h”
RCC→AHBENR[0] |= (0x1 « 5u); /* Enable GPIOF clock. */
RCC→APBENR[1] |= (0x1 « 10u); /* Enable ADC3 clock. */
/* Configure GPIO pin F.6 in analog input mode. */
GPIOA→MODER |= ~(0x3 « 6u); /* Set pin 6 to analog input mode. */
/* No ADC common configuration, ADCCLK ⇒ PCLK2 / 2 ⇒ 42 MHz. */
/* Configure ADC3 channel 4. */
ADC3→CR1 |= (0x3 « 24u); /* Set resolution to 6 bit. */
ADC3→SQR3 |= (4u « 0u); /* Channel 4 first in conversion sequence (SQ1). */
ADC3→SQR1 |= (0x0 « 20u); /* Set L to 0 → only 1 channel (SQ1) in sequence. */
ADC3→CR2 |= (0x1 « 0u); /* Enable ADC3. */
/* Start conversion */
uint32_t data;
ADC3→CR2 |= (0x1 « 30u); /* Start conversion. */
while (!(ADC3→SR & (0x1 « 1u))); /* Wait for EOC flag (end of conversion). */
data = ADC3→DR;
</code>
> 
Hardware Abstraction Layer**