The wakeup timer is a programmable 16 bit auto-reload down-counter.
The wakeup timer range can be extended to 17 bits.
The wakeup timer can be used to generate a periodic interrupt through the wakeup timer flag (WUTF). Additionally the WUTF flag can be output (through signals WKUP, RTC_ALARM and on to RTC_AF1) to pin PC13.
The wakeup timer clock input can be
After a reset the backup domain is write protected. The backup domain encompasses: RTC, LSE oscillator, backup SRAM, I/O pins PC13 to PC15 and PI8. The backup domain is powered through VBAT even if VDD is turned off.
Unlock access to backup domain:
DBP bit (disable backup protection) in PWR→CR.
After a backup domain reset (not a system reset) most of the RTC registers are write protected.
Disable the write protection by writing the unlock key to RTC→WPR:
0xCA to RTC→WPR.0x53 to RTC→WPR.
The RTC clock is disabled by default. Select a clock source and enable the RTC clock.
Make sure that the clock source is available while in power down mode.
RCC→BDCR.RCC→BDCR.To configure the auto wakeup timer proceed as follows:
RTC→CR.RTC→ISR.RTC→CR.RTC→WUTR.RTC→CR.
To use the wakeup interrupt, you need to configure the EXTI channel
and enable it in the NVIC:
RTC→ISR.Start the wakeup timer:
RTC→CR.Reenable RTC write protection:
0xff to RTC→WPR.
| WUCKSEL | 000 | fWUT ⇒ RTCCLK/16 (reset state) | 10x | fWUT ⇒ ck_spre (1Hz) |
| 001 | fWUT ⇒ RTCCLK/8 | |||
| 010 | fWUT ⇒ RTCCLK/4 | 11x | fWUT ⇒ ck_spre (1Hz), 216 added to WUTR | |
| 011 | fWUT ⇒ RTCCLK/2 | |||
| WUTE | 0 | Wake up timer disabled (reset state) | ||
| 1 | Wake up timer enabled | |||
| WUTIE | 0 | Wake up timer interrupt disabled (reset state) | ||
| 1 | Wake up timer interrupt enabled | |||
| WUTWF* | 0 | Wake up timer configuration not allowed | |
| 1 | Wake up timer configuration allowed | ||
| WUTF | Wake up timer flag is set by hardware when wakeup counter reaches 0 and cleared by software by writing 0. | ||
* This bit is set, after the WUTE bit (control register) has been set to 0, and reset by hardware.
| RTCEN* | 0 | RTC clock disabled |
| 1 | RTC clock enabled | |
| RTCSEL | 00 | No clock |
| 01 | LSE oscillator clock used as the RTC clock | |
| 10 | LSI oscillator clock used as the RTC clock | |
| 11 | HSE oscillator clock divided by a programmable prescaler(selection Through RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC clock |