Wake Up Timer

The wakeup timer is a programmable 16 bit auto-reload down-counter.
The wakeup timer range can be extended to 17 bits.




The wakeup timer can be used to generate a periodic interrupt through the wakeup timer flag (WUTF). Additionally the WUTF flag can be output (through signals WKUP, RTC_ALARM and on to RTC_AF1) to pin PC13.

The wakeup timer clock input can be

Programming Instructions

RTC register write protection

After a reset the backup domain is write protected. The backup domain encompasses: RTC, LSE oscillator, backup SRAM, I/O pins PC13 to PC15 and PI8. The backup domain is powered through VBAT even if VDD is turned off.
Unlock access to backup domain:

After a backup domain reset (not a system reset) most of the RTC registers are write protected.
Disable the write protection by writing the unlock key to RTC→WPR:

Enable RTC clock

The RTC clock is disabled by default. Select a clock source and enable the RTC clock.
Make sure that the clock source is available while in power down mode.

Setup wakeup timer

To configure the auto wakeup timer proceed as follows:

To use the wakeup interrupt, you need to configure the EXTI channel
and enable it in the NVIC:

Start the wakeup timer:

Reenable RTC write protection:


Configuration Registers

RTC_CR - Configuration register




WUCKSEL000fWUT ⇒ RTCCLK/16 (reset state)10xfWUT ⇒ ck_spre (1Hz)
001fWUT ⇒ RTCCLK/8
010fWUT ⇒ RTCCLK/411xfWUT ⇒ ck_spre (1Hz), 216 added to WUTR
011fWUT ⇒ RTCCLK/2
WUTE0Wake up timer disabled (reset state)
1Wake up timer enabled
WUTIE0Wake up timer interrupt disabled (reset state)
1Wake up timer interrupt enabled

RTC_WUTR - Wakeup timer register




Status Registers

RTC_ISR - Initialization and status register




WUTWF*0Wake up timer configuration not allowed
1Wake up timer configuration allowed
WUTFWake up timer flag is set by hardware when wakeup counter reaches 0 and cleared by software by writing 0.

* This bit is set, after the WUTE bit (control register) has been set to 0, and reset by hardware.

Back domain control register

RCC_BDCR - Back domain control register




RTCEN*0RTC clock disabled
1RTC clock enabled
RTCSEL00No clock
01LSE oscillator clock used as the RTC clock
10LSI oscillator clock used as the RTC clock
11HSE oscillator clock divided by a programmable prescaler(selection Through RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC clock