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Both sides previous revision Previous revision Next revision | Previous revision | ||
stm32:peripherals:timer_base [2022/12/27 17:48] – [SMCR] ruan | stm32:peripherals:timer_base [2023/10/19 09:49] (current) – frtt | ||
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===== Configuration Registers ===== | ===== Configuration Registers ===== | ||
- | ==== CR1 - Configuration register 1 ==== | + | ==== TIMx_CR1 |
- | + | ||
\\ {{timer_reg_cr1.svg}} \\ \\ | \\ {{timer_reg_cr1.svg}} \\ \\ | ||
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|::: | |::: | ||
//*This bit is readonly in center-aligned or encoder mode// \\ | //*This bit is readonly in center-aligned or encoder mode// \\ | ||
- | ==== DIER - DMA / Interrupt enable register ==== | + | |
+ | ==== TIMx_DIER | ||
\\ {{timer_reg_dier.svg}} \\ \\ | \\ {{timer_reg_dier.svg}} \\ \\ | ||
Line 31: | Line 30: | ||
|::: | |::: | ||
- | ==== SMCR - Slave mode control register ==== | + | ==== TIMx_SMCR |
\\ {{timer_reg_smcr.svg}} \\ \\ | \\ {{timer_reg_smcr.svg}} \\ \\ | ||
Line 55: | Line 54: | ||
|::: | |::: | ||
- | ==== PSC ==== | + | ==== TIMx_PSC - Prescaler register |
- | + | ||
- | Prescaler register | + | |
\\ {{timer_reg_psc.svg}} \\ \\ | \\ {{timer_reg_psc.svg}} \\ \\ | ||
- | ==== ARR ==== | + | ==== TIMx_ARR - Auto reload register |
- | + | ||
- | Auto reload register | + | |
\\ {{timer_reg_arr.svg}} \\ \\ | \\ {{timer_reg_arr.svg}} \\ \\ | ||
Line 69: | Line 64: | ||
===== Data Registers ===== | ===== Data Registers ===== | ||
- | ==== CNT ==== | + | ==== TIMx_CNT - Count register |
- | + | ||
- | Count register | + | |
\\ {{timer_reg_cnt.svg}} \\ \\ | \\ {{timer_reg_cnt.svg}} \\ \\ | ||
Line 77: | Line 70: | ||
===== Programming Example ===== | ===== Programming Example ===== | ||
- | The code snippet | + | The code snippet |
<code c> | <code c> | ||
Line 85: | Line 78: | ||
/* configure timer */ | /* configure timer */ | ||
- | TIM2-> | + | TIM2-> |
- | TIM2-> | + | TIM2-> |
TIM2-> | TIM2-> | ||
</ | </ | ||
\\ | \\ |