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| Both sides previous revision Previous revision Next revision | Previous revision | ||
| stm32:peripherals:timer_base [2022/12/27 17:48] – [CR1] ruan | stm32:peripherals:timer_base [2023/10/19 09:49] (current) – frtt | ||
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| Line 5: | Line 5: | ||
| ===== Configuration Registers ===== | ===== Configuration Registers ===== | ||
| - | ==== CR1 - Configuration register 1 ==== | + | ==== TIMx_CR1 |
| - | + | ||
| \\ {{timer_reg_cr1.svg}} \\ \\ | \\ {{timer_reg_cr1.svg}} \\ \\ | ||
| Line 19: | Line 17: | ||
| |::: | |::: | ||
| //*This bit is readonly in center-aligned or encoder mode// \\ | //*This bit is readonly in center-aligned or encoder mode// \\ | ||
| - | ==== DIER ==== | ||
| - | DMA / Interrupt enable register | + | ==== TIMx_DIER - DMA / Interrupt enable register |
| \\ {{timer_reg_dier.svg}} \\ \\ | \\ {{timer_reg_dier.svg}} \\ \\ | ||
| Line 33: | Line 30: | ||
| |::: | |::: | ||
| - | ==== SMCR ==== | + | ==== TIMx_SMCR - Slave mode control register |
| - | + | ||
| - | Slave mode control register | + | |
| \\ {{timer_reg_smcr.svg}} \\ \\ | \\ {{timer_reg_smcr.svg}} \\ \\ | ||
| Line 59: | Line 54: | ||
| |::: | |::: | ||
| - | ==== PSC ==== | + | ==== TIMx_PSC - Prescaler register |
| - | + | ||
| - | Prescaler register | + | |
| \\ {{timer_reg_psc.svg}} \\ \\ | \\ {{timer_reg_psc.svg}} \\ \\ | ||
| - | ==== ARR ==== | + | ==== TIMx_ARR - Auto reload register |
| - | + | ||
| - | Auto reload register | + | |
| \\ {{timer_reg_arr.svg}} \\ \\ | \\ {{timer_reg_arr.svg}} \\ \\ | ||
| Line 73: | Line 64: | ||
| ===== Data Registers ===== | ===== Data Registers ===== | ||
| - | ==== CNT ==== | + | ==== TIMx_CNT - Count register |
| - | + | ||
| - | Count register | + | |
| \\ {{timer_reg_cnt.svg}} \\ \\ | \\ {{timer_reg_cnt.svg}} \\ \\ | ||
| Line 81: | Line 70: | ||
| ===== Programming Example ===== | ===== Programming Example ===== | ||
| - | The code snippet | + | The code snippet |
| <code c> | <code c> | ||
| Line 89: | Line 78: | ||
| /* configure timer */ | /* configure timer */ | ||
| - | TIM2-> | + | TIM2-> |
| - | TIM2-> | + | TIM2-> |
| TIM2-> | TIM2-> | ||
| </ | </ | ||
| \\ | \\ | ||