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stm32:peripherals:rtc_wakeup [2017/08/24 13:05] – [Wake Up Timer] ruanstm32:peripherals:rtc_wakeup [2022/12/27 18:42] (current) – ruan
Line 15: Line 15:
 ==== RTC register write protection ==== ==== RTC register write protection ====
  
-After a reset the backup domain is write protected. \\+After a reset the backup domain is write protected. The backup domain encompasses: RTC, LSE oscillator, backup SRAM, I/O pins PC13 to PC15 and PI8. The backup domain is powered through VBAT even if VDD is turned off.\\
 Unlock access to backup domain: Unlock access to backup domain:
   * Set the ''DBP'' bit (disable backup protection) in ''PWR->CR''.   * Set the ''DBP'' bit (disable backup protection) in ''PWR->CR''.
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   * Disable wakeup timer in ''RTC->CR''.   * Disable wakeup timer in ''RTC->CR''.
   * Wait until configuration of RTC is allowed. \\ Check corresponding bit in ''RTC->ISR''.   * Wait until configuration of RTC is allowed. \\ Check corresponding bit in ''RTC->ISR''.
-  * Program reload value in ''RTC->WUTR''. 
   * Program prescaler value in ''RTC->CR''.   * Program prescaler value in ''RTC->CR''.
 +  * Program reload value in ''RTC->WUTR''.
   * Enable wakeup interrupt in ''RTC->CR''.   * Enable wakeup interrupt in ''RTC->CR''.
  
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 ===== Configuration Registers ===== ===== Configuration Registers =====
  
-==== RTC_CR ==== +==== RTC_CR - Configuration register ====
- +
-Configuration register+
  
 \\ {{rtc_reg_cr.svg}} \\ \\ \\ {{rtc_reg_cr.svg}} \\ \\
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 |:::|1|Wake up timer interrupt enabled|| |:::|1|Wake up timer interrupt enabled||
  
-==== RTC_WUTR ==== +==== RTC_WUTR - Wakeup timer register ====
- +
-Wakeup timer register+
  
 \\ {{rtc_reg_wutr.svg}} \\ \\ \\ {{rtc_reg_wutr.svg}} \\ \\
Line 81: Line 77:
 ===== Status Registers ===== ===== Status Registers =====
  
-==== RTC_ISR ==== +==== RTC_ISR - Initialization and status register ====
- +
-Initialization and status register+
  
 \\ {{rtc_reg_isr.svg}} \\ \\ \\ {{rtc_reg_isr.svg}} \\ \\
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 |WUTWF*|0|Wake up timer configuration not allowed| |WUTWF*|0|Wake up timer configuration not allowed|
 |:::|1|Wake up timer configuration allowed| |:::|1|Wake up timer configuration allowed|
 +|WUTF||Wake up timer flag is set by hardware when wakeup counter reaches 0 and cleared by software by writing 0.||
 * This bit is set, after the WUTE bit (control register) has been set to 0, and reset by hardware. * This bit is set, after the WUTE bit (control register) has been set to 0, and reset by hardware.
 +
 +===== Back domain control register =====
 +
 +==== RCC_BDCR - Back domain control register ====
 +
 +\\ {{rcc_reg_bdcr.svg}} \\ \\ 
 +
 +|< 100% 5em 5em >|
 +|RTCEN*|0|RTC clock disabled|
 +|:::|1|RTC clock enabled|
 +|RTCSEL|00|No clock|
 +|:::|01|LSE oscillator clock used as the RTC clock|
 +|:::|10|LSI oscillator clock used as the RTC clock|
 +|:::|11|HSE oscillator clock divided by a programmable prescaler(selection Through RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC clock|
 +
  • stm32/peripherals/rtc_wakeup.1503579932.txt.gz
  • Last modified: 2017/08/24 13:05
  • by ruan