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| Both sides previous revision Previous revision Next revision | Previous revision | ||
| stm32:peripherals:rcc [2016/02/29 09:27] – feur | stm32:peripherals:rcc [2022/12/27 19:28] (current) – ruan | ||
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| - | ====== Reset and Clock Control ====== | + | ====== Reset and Clock Control |
| - | {{clock_complete.svg?350em}} | + | These registers allow to configure the system clock and enable / disable peripherals. |
| + | * [[stm32: | ||
| + | * [[stm32: | ||
| + | \\ {{clock_complete.svg}} \\ \\ | ||
| - | ===== Peripheral Configuration Registers ===== | ||
| - | \\ | ||
| - | |||
| - | ==== AHB1 Peripherals ==== | ||
| - | |||
| - | \\ {{clock_reg_ahb1_r.svg}} \\ \\ | ||
| - | |||
| - | ==== AHB2 Peripherals ==== | ||
| - | |||
| - | \\ {{clock_reg_ahb2_r.svg}} \\ \\ | ||
| - | |||
| - | ==== AHB3 Peripherals ==== | ||
| - | |||
| - | \\ {{clock_reg_ahb3_r.svg}} \\ \\ | ||
| - | |||
| - | ==== APB1 Peripherals ==== | ||
| - | |||
| - | \\ {{clock_reg_apb1_r.svg}} \\ \\ | ||
| - | |||
| - | ==== APB2 Peripherals ==== | ||
| - | |||
| - | \\ {{clock_reg_apb2_r.svg}} \\ \\ | ||
| - | |||
| - | ==== Register Description ==== | ||
| - | \\ | ||
| - | === xxxxENR === | ||
| - | |||
| - | |< 100% 5em 5em >| | ||
| - | |zEN|0|Peripheral clock disabled| | ||
| - | |zEN|1|Peripheral clock enabled| | ||
| - | |||
| - | === xxxxLPENR === | ||
| - | |||
| - | |< 100% 5em 5em >| | ||
| - | |zLPEN|0|Peripheral clock disabled during sleep mode| | ||
| - | |zLPEN|1|Peripheral clock enabled during sleep mode| | ||
| - | |||
| - | === xxxxRSTR === | ||
| - | |||
| - | |< 100% 5em 5em >| | ||
| - | |zLPEN|0|Peripheral **not** reset| | ||
| - | |zLPEN|1|Resets peripheral| | ||
| - | |||
| - | |||
| - | ===== Legend ===== | ||
| - | |||
| - | \\ {{legende.svg}} \\ \\ | ||