Differences

This shows you the differences between two versions of the page.

--- stm32:peripherals:pwr [2016/03/01 06:58] – created feur
+++ stm32:peripherals:pwr [2022/12/27 18:58] (current) – [PWR→CR] ruan
@@ Line 1: / Line 1: @@
 ====== Power Controller ======
-{{ power_complete.svg?350em}}
 The STM32F429ZI requires a voltage supply V<sub>DD</sub> of 1,8..3,6 V to operate. \\
-A linear voltage regulator is used to generate the 1,2 V internally needed for the CPU. \\ \\
+A linear voltage regulator is used to generate the 1,2 V internally needed for the CPU. \\
 The real time clock, backup registers and backup RAM can be powered by V<sub>BAT</sub>. \\
+\\ {{power_complete.svg}} \\ \\
 ===== Features =====
@@ Line 16: / Line 15: @@
 \\
-===== 1,2 V Domain =====
+===== Low Power Modes =====
+The following low power modes are vailable:
+  * The [[pwr_sleep|SLEEP]] mode offers some power reduction and fast wake up times.
+  * The [[pwr_stop|STOP]] mode offers more power reduction, at the cost of a slower wake up times.
+  * The [[pwr_standby|STANDBY]] (and VBAT) mode saves the most energy, at the cost of an even slower wake up time.
+The power reduction is accomplished by switching off different parts of the hardware. \\
+Which part is available in which mode is shown in the tables below. \\
+\\
+=== Clocks ===
+|< 45em 15em 10em >|
+| ^  SLEEP  ^  STOP  ^  STANDBY  |
+^ CPU clock |  disabled  |  disabled  |  disabled  |
+^ Peripheral clocks |  on / off  |  on / off  |  disabled  |
+^ RTC clock |  on / off  |  on / off  |  on / off  |
+\\
+=== Clock Sources ===
+|< 45em 15em 10em >|
+| ^  SLEEP  ^  STOP  ^  STANDBY  |
+^ Low Speed (Int. / Ext.) |  on / off  |  on / off  |  on / off  |
+^ High Speed (Int. / Ext.) |  on / off  |  disabled  |  disabled  |
+^ PLL Oscillator |  on / off  |  disabled  |  disabled  |
+\\
+=== Voltage Regulators ===
+|< 45em 15em 10em >|
+| ^  SLEEP  ^  STOP  ^  STANDBY  |
+^ Flash Power Down |  disabled  |  on / off  |  disabled  |
+^ 1,2V Domain (Normal) |  Main  |  Main \\ or \\ Low Power  |  disabled  |
+^ 1,2V Domain (Underdrive)* |  disabled  |:::|  disabled  |
+^ Backup Domain |  on / off  |  on / off  |  on / off  |
+* Underdrive mode of 1,2V domain voltage regulator only possible if Flash power down enabled. \\
+\\
+=== SRAM / Registers ===
+|< 45em 15em 10em >|
+| ^  SLEEP  ^  STOP  ^  STANDBY  |
+^ Regular SRAM |  on  |  on  |  disabled  |
+^ Regular Registers |  on  |  on  |  disabled  |
+^ Backup SRAM |  on / off  |  on / off  |  on / off  |
+^ Backup Registers |  on / off  |  on / off  |  on / off  |
+\\
+===== Configuration Registers =====
+==== PWR→CR - Configuration register ====
+\\ {{power_reg_cr.svg}} \\ \\
-\\ {{power_1.2V.svg}} \\ \\
+|< 100% 5em 5em >|
+|LPDS|0|Main voltage regulater used in STOP mode|
+|:::|1|Low power regulator used in STOP mode|
+|LPUDS|0|Low power regulator **on** if LPDS bit set in STOP mode|
+|:::|1|Low power regulator in under-drive mode if LPDS bit set in STOP mode|
+|PDDS|0|Enter STOP mode when CPU enters deep sleep|
+|:::|1|Enter STANDBY mode when CPU enters deep sleep|
+|FPDS|0|Flash memory **not** in power down mode in STOP mode|
+|:::|1|Flash memory in power down mode in STOP mode|