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| stm32:peripherals:dma_connection [2016/09/22 09:31] – feur | stm32:peripherals:dma_connection [2022/12/28 07:53] (current) – [Periphery/Memory Interface] ruan | ||
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| ====== DMA Connections ====== | ====== DMA Connections ====== | ||
| - | ===== AHB Bus Matrix ===== | + | Each DMA controller is connected to the rest of the system in a different way. \\ |
| + | For memory to memory transfers you should use the DMA controller 2! \\ | ||
| - | \\ {{ahb_bus_matrix.png?700em}} \\ \\ | + | \\ {{dma1_matrix.svg?350em}} {{dma2_matrix.svg? |
| - | ===== DMA request mapping ===== | ||
| - | ==== DMA1 ==== | + | ===== DMA controller 1 ===== |
| + | |||
| + | ==== Peripheral Interface ==== | ||
| + | |||
| + | On the peripheral interface the following marked peripherals are accessible. \\ | ||
| + | The <color red> | ||
| + | |||
| + | \\ {{dma1_periphery.svg? | ||
| |< 100% 7em >| | |< 100% 7em >| | ||
| ^ ^ Stream 0 ^ Stream 1 ^ Stream 2 ^ Stream 3 ^ Stream 4 ^ Stream 5 ^ Stream 6 ^ Stream 7 ^ | ^ ^ Stream 0 ^ Stream 1 ^ Stream 2 ^ Stream 3 ^ Stream 4 ^ Stream 5 ^ Stream 6 ^ Stream 7 ^ | ||
| Line 13: | Line 21: | ||
| ^ Channel 1 | I2C1 RX | | TIM7 Up | | TIM7 Up | I2C1 RX | I2C1 TX | I2C1 TX | | ^ Channel 1 | I2C1 RX | | TIM7 Up | | TIM7 Up | I2C1 RX | I2C1 TX | I2C1 TX | | ||
| ^ Channel 2 | TIM4 Ch. 1 | | I2S3 Ext RX | TIM4 Ch. 2 | I2S2 Ext TX | I2S3 Ext TX | TIM4 Up | TIM4 Ch. 3 | | ^ Channel 2 | TIM4 Ch. 1 | | I2S3 Ext RX | TIM4 Ch. 2 | I2S2 Ext TX | I2S3 Ext TX | TIM4 Up | TIM4 Ch. 3 | | ||
| - | ^ Channel 3 | | | | | | | | | | + | ^ Channel 3 | I2S3 Ext RX | TIM2 Up \\ TIM2 Ch. 3 | I2C3 RX | I2S2 Ext RX | I2C3 TX | TIM2 Ch. 1 | TIM2 Ch. 2 \\ TIM2 Ch. 4 | TIM2 Up \\ TIM2 Ch. 4 | |
| - | ^ Channel 4 | | | | | | | | | | + | ^ Channel 4 | UART5 RX | USART3 RX | UART4 RX | USART3 TX | UART4 TX | USART2 RX | USART2 TX | UART5 TX | |
| - | ^ Channel 5 | | | | | | | | | | + | ^ Channel 5 | UART8 TX | UART7 TX | TIM3 Ch. Up \\ TIM3 Ch. 4 | UART7 RX | TIM3 TRG \\ TIM3 Ch. 1 | TIM3 Ch. 2 | UART8 RX | TIM3 Ch. 3 | |
| - | ^ Channel 6 | | | | | | | | | | + | ^ Channel 6 | TIM5 Up \\ TIM5 Ch. 3 | TIM5 TRG \\ TIM5 Ch. 4 | TIM5 Ch. 1 | TIM5 TRG \\ TIM5 Ch. 4 | TIM5 Ch. 2 | | TIM5 Up | | |
| - | ^ Channel 7 | | | | | | | | | | + | ^ Channel 7 | | TIM6 Up | I2C2 RX | I2C2 RX | USART3 TX | DAC1 | DAC2 | I2C2 TX | |
| - | ==== DMA2 ==== | + | ==== Memory Interface |
| + | |||
| + | On the memory interface the following marked peripherals are accessible. \\ | ||
| + | |||
| + | \\ {{dma1_memory.svg? | ||
| + | |||
| + | ===== DMA controller 2 ===== | ||
| + | |||
| + | ==== Peripheral/ | ||
| + | |||
| + | This DMA controller can access the same peripherals on the memory interface as on the peripheral interface. \\ | ||
| + | The <color red> | ||
| + | |||
| + | \\ {{dma2_mem_per.svg? | ||
| + | |||
| + | |< 100% 7em >| | ||
| + | ^ ^ Stream 0 ^ Stream 1 ^ Stream 2 ^ Stream 3 ^ Stream 4 ^ Stream 5 ^ Stream 6 ^ Stream 7 ^ | ||
| + | ^ Channel 0 | ADC1 | SAI1 A | TIM8 Ch. 1 \\ TIM8 Ch. 2 \\ TIM8 Ch. 3 | SAI1 A | ADC1 | SAI1 B | TIM1 Ch. 1 \\ TIM1 Ch. 2 \\ TIM1 Ch. 3 | | | ||
| + | ^ Channel 1 | | DCMI | ADC2 | ADC2 | SAI1 B | SPI6 TX | SPI6 RX | DCMI | | ||
| + | ^ Channel 2 | ADC3 | ADC3 | | SPI5 RX | SPI5 TX | CRYP Out | CRYP In | HASH In | | ||
| + | ^ Channel 3 | SPI1 RX | | SPI1 RX | SPI1 TX | | SPI1 TX | | | | ||
| + | ^ Channel 4 | SPI4 RX | SPI4 TX | USART1 RX | SDIO | | USART1 RX | SDIO | USART1 TX | | ||
| + | ^ Channel 5 | | USART6 RX | USART6 RX | SPI4 RX | SPI4 TX | | USART6 TX | USART6 TX | | ||
| + | ^ Channel 6 | TIM1 TRG | TIM1 Ch. 1 | TIM1 Ch. 2 | TIM1 Ch. 1 | TIM1 TRG \\ TIM1 COM \\ TIM1 Ch. 4 | TIM1 Up | TIM1 Ch. 3 | | | ||
| + | ^ Channel 7 | | TIM8 Up | TIM8 Ch. 1 | TIM8 Ch. 2 | TIM8 Ch. 3 | SPI5 RX | SPI5 TX | TIM8 TRG \\ TIM8 COM \\ TIM8 Ch. 4 | | ||