Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
stm32:peripherals:dma [2022/12/28 07:48] – ruanstm32:peripherals:dma [2022/12/28 07:50] (current) – ruan
Line 15: Line 15:
 ===== Configuration Registers ===== ===== Configuration Registers =====
  
-==== SxCR - Stream X configuration register ====+==== DMA_SxCR - Stream X configuration register ====
  
 \\ {{dma_reg_sxcr.svg}} \\ \\ \\ {{dma_reg_sxcr.svg}} \\ \\
Line 40: Line 40:
 * Only writeable if EN = '0' \\ \\ * Only writeable if EN = '0' \\ \\
  
-==== SxPAR - Stream X peripheral address register ====+==== DMA_SxPAR - Stream X peripheral address register ====
  
 \\ {{dma_reg_sxpar.svg}} \\ \\ \\ {{dma_reg_sxpar.svg}} \\ \\
Line 47: Line 47:
 |NDT|xxx|Number of data items to be transfered.| |NDT|xxx|Number of data items to be transfered.|
  
-==== SxM0AR - Stream X memory 0 address register====+==== DMA_SxM0AR - Stream X memory 0 address register====
  
 \\ {{dma_reg_sxm0ar.svg}} \\ \\ \\ {{dma_reg_sxm0ar.svg}} \\ \\
Line 54: Line 54:
 |M0A|xxx|Base address of memory 0.| |M0A|xxx|Base address of memory 0.|
  
-==== SxM1AR - Stream X memory 1 address register ====+==== DMA_SxM1AR - Stream X memory 1 address register ====
  
 \\ {{dma_reg_sxm1ar.svg}} \\ \\ \\ {{dma_reg_sxm1ar.svg}} \\ \\
Line 61: Line 61:
 |M1A|xxx|Base address of memory 1.| |M1A|xxx|Base address of memory 1.|
  
-==== SxNDTR - Stream X number of data register ====+==== DMA_SxNDTR - Stream X number of data register ====
  
 \\ {{dma_reg_sxndtr.svg}} \\ \\ \\ {{dma_reg_sxndtr.svg}} \\ \\
  • stm32/peripherals/dma.1672213706.txt.gz
  • Last modified: 2022/12/28 07:48
  • by ruan