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| Both sides previous revision Previous revision Next revision | Previous revision | ||
| stm32:peripherals:dma [2022/12/28 07:47] – [Programming Example] ruan | stm32:peripherals:dma [2022/12/28 07:50] (current) – ruan | ||
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| ===== Configuration Registers ===== | ===== Configuration Registers ===== | ||
| - | ==== SxCR ==== | + | ==== DMA_SxCR - Stream X configuration register |
| - | + | ||
| - | Stream X configuration register | + | |
| \\ {{dma_reg_sxcr.svg}} \\ \\ | \\ {{dma_reg_sxcr.svg}} \\ \\ | ||
| Line 42: | Line 40: | ||
| * Only writeable if EN = ' | * Only writeable if EN = ' | ||
| - | ==== SxPAR ==== | + | ==== DMA_SxPAR - Stream X peripheral address register |
| - | + | ||
| - | Stream X peripheral address register | + | |
| \\ {{dma_reg_sxpar.svg}} \\ \\ | \\ {{dma_reg_sxpar.svg}} \\ \\ | ||
| Line 51: | Line 47: | ||
| |NDT|xxx|Number of data items to be transfered.| | |NDT|xxx|Number of data items to be transfered.| | ||
| - | ==== SxM0AR ==== | + | ==== DMA_SxM0AR - Stream X memory 0 address register==== |
| - | + | ||
| - | Stream X memory 0 address register | + | |
| \\ {{dma_reg_sxm0ar.svg}} \\ \\ | \\ {{dma_reg_sxm0ar.svg}} \\ \\ | ||
| Line 60: | Line 54: | ||
| |M0A|xxx|Base address of memory 0.| | |M0A|xxx|Base address of memory 0.| | ||
| - | ==== SxM1AR ==== | + | ==== DMA_SxM1AR - Stream X memory 1 address register |
| - | + | ||
| - | Stream X memory 1 address register | + | |
| \\ {{dma_reg_sxm1ar.svg}} \\ \\ | \\ {{dma_reg_sxm1ar.svg}} \\ \\ | ||
| Line 69: | Line 61: | ||
| |M1A|xxx|Base address of memory 1.| | |M1A|xxx|Base address of memory 1.| | ||
| - | ==== SxNDTR ==== | + | ==== DMA_SxNDTR - Stream X number of data register |
| - | + | ||
| - | Stream X number of data register | + | |
| \\ {{dma_reg_sxndtr.svg}} \\ \\ | \\ {{dma_reg_sxndtr.svg}} \\ \\ | ||