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| Both sides previous revision Previous revision Next revision | Previous revision | ||
| stm32:peripherals:dac [2016/03/01 14:15] – feur | stm32:peripherals:dac [2022/12/28 08:14] (current) – ruan | ||
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| \\ | \\ | ||
| - | ===== Programming Example ===== | + | |
| ===== Configuration Register ===== | ===== Configuration Register ===== | ||
| - | ==== CR ==== | + | ==== DAC_CR |
| \\ {{dac_reg_cr.svg}} \\ \\ | \\ {{dac_reg_cr.svg}} \\ \\ | ||
| Line 35: | Line 35: | ||
| ===== Status Register ===== | ===== Status Register ===== | ||
| - | ==== SR ==== | + | ==== DAC_SR |
| \\ {{dac_reg_sr.svg}} \\ \\ | \\ {{dac_reg_sr.svg}} \\ \\ | ||
| |< 100% 5em >| | |< 100% 5em >| | ||
| - | |||| | + | |DMAUDRx|0|No DMA underrun error of channel x occured| |
| + | |:::|1|DMA underrun error of channel x occured| | ||
| - | ===== Data Registers ===== | + | * Writing 1 to clear flag. \\ \\ |
| - | ==== DHR8Rx | + | ===== Data Registers ===== |
| - | DHR8R1, DHR8R2 and DHR8RD registers | + | ==== DAC_DHR8Rx - DHR8R1, DHR8R2 and DHR8RD registers |
| \\ {{dac_reg_dhr8r_.svg}} \\ \\ | \\ {{dac_reg_dhr8r_.svg}} \\ \\ | ||
| - | ==== DHR12Rx ==== | + | ==== DAC_DHR12Rx - DHR12R1, DHR12R2 and DHR12RD registers |
| - | + | ||
| - | DHR12R1, DHR12R2 and DHR12RD registers | + | |
| \\ {{dac_reg_dhr12r_.svg}} \\ \\ | \\ {{dac_reg_dhr12r_.svg}} \\ \\ | ||
| - | ==== DHR12Lx ==== | + | ==== DAC_DHR12Lx - DHR12L1, DHR12L2 and DHR12LD registers |
| - | + | ||
| - | DHR12L1, DHR12L2 and DHR12LD registers | + | |
| \\ {{dac_reg_dhr12l_.svg}} \\ \\ | \\ {{dac_reg_dhr12l_.svg}} \\ \\ | ||
| - | ==== DORx ==== | + | ==== DAC_DORx - Data output register |
| - | + | ||
| - | Data output register | + | |
| \\ {{dac_reg_dor_.svg}} \\ \\ | \\ {{dac_reg_dor_.svg}} \\ \\ | ||
| - | |||
| - | ===== Legend ===== | ||
| - | |||
| - | \\ {{legend.svg}} \\ \\ | ||