Differences

This shows you the differences between two versions of the page.

--- stm32:peripherals:adc [2022/12/23 12:27] – ruan
+++ stm32:peripherals:adc [2022/12/28 08:11] (current) – ruan
@@ Line 17: / Line 17: @@
 ===== Configuration Registers =====
-==== ADCCOM→CCR ====
+==== ADC_CCR - Common control register ====
-Common control register
 \\ {{adc_reg_ccr.svg}} \\ \\
@@ Line 29: / Line 27: @@
 |:::|11|ADCCLK => f<sub>PCLK2</sub> / 8|
-==== ADCx→CRx ====
+==== ADCx_CR1 - Configuration register 1 ====
-=== ADCx→CR1 ===
-Configuration register 1
 \\ {{adc_reg_cr1.svg}} \\ \\
@@ Line 45: / Line 39: @@
 |:::|11|6 bit, 9 ADCCLK cycles conversion time|
-=== ADCx→CR2 ===
+==== ADCx_CR2 - Configuration register 2 ====
-Configuration register 2
 \\ {{adc_reg_cr2.svg}} \\ \\
@@ Line 73: / Line 65: @@
 |:::|1|Start conversion of regular channels|||
-==== ADCx→SMPRx ====
+==== ADCx_SMPR1 - Sample time register 1 ====
-=== ADCx→SMPR1 ===
-Sample time register 1
 \\ {{adc_reg_smpr1.svg}} \\ \\
-=== ADCx→SMPR2 ===
+==== ADCx_SMPR2 - Sample time register 2 ====
-Sample time register 2
 \\ {{adc_reg_smpr2.svg}} \\ \\
@@ Line 95: / Line 81: @@
 |:::|011|56 cycles sampling time|111|480 cycles sampling time|
-==== ADCx→SQRx ====
+==== ADCx_SQR1 - Sequence register 1 ====
-=== ADCx→SQR1 ===
-Sequence register 1
 \\ {{adc_reg_sqr1.svg}} \\ \\
-=== ADCx→SQR2 ===
+==== ADCx_SQR2 - Sequence register 2 ====
-Sequence register 2
 \\ {{adc_reg_sqr2.svg}} \\ \\
-=== ADCx→SQR3 ===
+==== ADCx_SQR3 - Sequence register 3 ====
-Sequence register 3
 \\ {{adc_reg_sqr3.svg}} \\ \\
@@ Line 126: / Line 104: @@
 ===== Status Register =====
-==== ADCx→SR ====
+==== ADCx_SR - Status register ====
-Status register
 \\ {{adc_reg_sr.svg}} \\ \\
@@ Line 136: / Line 112: @@
 ===== Data Register =====
-==== ADCx→DR ====
+==== ADCx_DR - Data register ====
-Data register
 \\ {{adc_reg_dr.svg}} \\ \\
 * Register is read only \\ \\
-===== Legend =====
-\\ {{legende.svg}} \\ \\
-> {{logo_hal.svg?72px |}} **Hardware Abstraction Layer**
-> [[https://ennis.zhaw.ch/hal/structreg__adc__t.html | Register Types]]
-> [[https://ennis.zhaw.ch/hal/hal__adc_8h.html | InES ADC HAL Interface]]
-\\
 ===== Programming Example =====
@@ Line 178: / Line 143: @@
 data = ADC3->DR;
 </code>
-\\===== Programming Example =====
+\\
-<code c>
-#include "reg_stm32f4xx.h"
-RCC->AHBENR[0] |= (0x1 <<  5u);         /* Enable GPIOF clock. */
-RCC->APBENR[1] |= (0x1 << 10u);         /* Enable ADC3 clock. */
-/* Configure GPIO pin F.6 in analog input mode. */
-GPIOA->MODER |= ~(0x3 << 6u);         /* Set pin 6 to analog input mode. */
-/* No ADC common configuration, ADCCLK => PCLK2 / 2 => 42 MHz. */
-/* Configure ADC3 channel 4. */
-ADC3->CR1 |= (0x3 << 24u);            /* Set resolution to 6 bit. */
-ADC3->SQR3 |= (4u << 0u);             /* Channel 4 first in conversion sequence (SQ1). */
-ADC3->SQR1 |= (0x0 << 20u);           /* Set L to 0 -> only 1 channel (SQ1) in sequence. */
-ADC3->CR2 |= (0x1 << 0u);             /* Enable ADC3. */
-/* Start conversion */
-uint32_t data;
-ADC3->CR2 |= (0x1 << 30u);            /* Start conversion. */
-while (!(ADC3->SR & (0x1 << 1u)));    /* Wait for EOC flag (end of conversion). */
-data = ADC3->DR;
-</code>
-\\