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ctboard:peripherals:gpio [2016/02/11 07:26] – feur | ctboard:peripherals:gpio [2017/08/29 09:19] (current) – [GPIO] ruan | ||
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====== GPIO ====== | ====== GPIO ====== | ||
- | The CT Board offers on the 4 general | + | The CT Board offers on the 4 general |
- | * 4 general | + | * 4 general |
* 32 memory mapped output pins | * 32 memory mapped output pins | ||
* 32 memory mapped input pins | * 32 memory mapped input pins | ||
- | * 2 general | + | * 2 general |
* External interface to [[memory_bus|SRAM bus]]. | * External interface to [[memory_bus|SRAM bus]]. | ||
+ | \\ | ||
- | ===== GPIO over CPLD ===== | + | ===== Functions |
- | Each of the 4 GPIO ports contains 8 ouput and 8 input pins. The ports are not as fast as the integrated [[stm32:peripherals: | + | These modes are available: |
- | > {{ctboard: | + | * [[gpio_cpld|GPIO over CPLD]] for input / output on ports P1..4. |
- | > Supported | + | |
- | + | ||
- | ==== Registers ==== | + | |
- | + | ||
- | === Input === | + | |
- | + | ||
- | \\ {{ ctboard_gpio_pinout.svg? | + | |
- | | + | |
- | + | ||
- | === Output === | + | |
- | + | ||
- | The Registers are read / write. | + | |
- | + | ||
- | \\ {{ctboard_gpio_output_reg.svg}} \\ \\ | + | |
- | + | ||
- | ==== Diagram ==== | + | |
- | + | ||
- | \\ {{ctboard_gpio_cpld.svg}} \\ \\ | + | |
- | + | ||
- | ===== GPIO over MCU ===== | + | |
- | + | ||
- | These two ports are directly connected to the [[stm32: | + | |
- | All [[stm32: | + | |
- | + | ||
- | > {{ctboard_mode_no.svg? | + | |
- | > Supported modes: Available in all modes. | + | |
- | + | ||
- | ==== Diagram ==== | + | |
- | + | ||
- | > Only pins 0..11 are connected to P5 / P6! The other 4 pins are used for 5V, 3.3V and GND. | + | |
- | + | ||
- | \\ {{ctboard_gpio_stm32.svg}} \\ \\ | + | |