Differences

This shows you the differences between two versions of the page.

--- ctboard:peripherals:gpio [2016/01/27 13:12] – feur
+++ ctboard:peripherals:gpio [2017/08/29 09:19] (current) – [GPIO] ruan
@@ Line 1: / Line 1: @@
 ====== GPIO ======
-The CT Board offers on the 4 general purpouse ports the following functions:
+The CT Board offers on the 4 general purpose ports the following functions:
-  * 4 general purpouse I/O ports
+  * 4 general purpose I/O ports
     * 32 memory mapped output pins
     * 32 memory mapped input pins
-  * 2 general purpouse I/O ports, directly connected to MCUs [[stm32:peripherals:gpio|Port A and B]]
+  * 2 general purpose I/O ports, directly connected to MCUs [[stm32:peripherals:gpio|Port A and B]]
-  * External interface to SRAM bus.
+  * External interface to [[memory_bus|SRAM bus]].
+\\
-===== GPIO over CPLD =====
+===== Functions =====
-Each of the 4 GPIO ports contains 8 ouput and 8 input pins. The ports are not as fast as the integrated [[stm32:peripherals:gpio|GPIO ports]] of the microcontroller. \\ \\
+These modes are available:
-> {{ctboard_mode_1.svg?48px }} Please make sure the CT Board is in the correct mode.
+  * [[gpio_cpld|GPIO over CPLD]] for input / output on ports P1..4.
-> Supported mode: **1**
+  * [[gpio_mcu|GPIO over MCU]] for input / output on ports P5 / P6.
-==== Registers ====
-=== Input ===
-The Registers are read only.
-|< 100% 10em >|
-^  Address  ^  Bit 7  ^  Bit 6  ^  Bit 5  ^  Bit 4  ^  Bit 3  ^  Bit 2  ^  Bit 1  ^  Bit 0  ^
-^  0x6000'0410  |  P1 Input  ||||||||
-^  0x6000'0411  |  P2 Input  ||||||||
-^  0x6000'0412  |  P3 Input  ||||||||
-^  0x6000'0413  |  P4 Input  ||||||||
-=== Output ===
-The Registers are read / write.
-|< 100% 10em >|
-^  Address  ^  Bit 7  ^  Bit 6  ^  Bit 5  ^  Bit 4  ^  Bit 3  ^  Bit 2  ^  Bit 1  ^  Bit 0  ^
-^  0x6000'0400  |  P1 Output  ||||||||
-^  0x6000'0401  |  P2 Output  ||||||||
-^  0x6000'0402  |  P3 Output  ||||||||
-^  0x6000'0403  |  P4 Output  ||||||||
-==== Diagram ====
-\\ {{ctboard_gpio_cpld.svg}} \\ \\
-\\ {{ ctboard_gpio_pinout.svg?400em }} \\ \\
-===== GPIO over MCU =====
-These two ports are directly connected to the [[stm32:peripherals:gpio|GPIO ports A and B]] on the microcontroller. \\
-All [[stm32:peripherals:gpio#alternate_functions|functions]] of theese GPIO ports are available. \\ \\
-> {{ctboard_mode_no.svg?48px }} This functionality is independent of the CT Board mode.
-> Supported modes: Available in all modes.
-==== Diagram ====
-> Only pins 0..11 are connected to P5 / P6! The other 4 pins are used for 5V, 3.3V and GND.
-\\ {{ctboard_gpio_stm32.svg}} \\ \\
-===== External Memory Bus =====
-The CT Board is connected to the microcontroller over SRAM interface. This interface is also available on ports P1..4. \\ \\
-==== Full Bus ====
-The full interface is connected. \\ \\
-> {{ctboard_mode_2.svg?48px }} This functionality is independent of the CT Board mode.
-> Supported modes: **2**.
-=== Pin Out ===
-== P1 ==
-|< 100% 10em >|
-^  Pin 2  ^  Pin 4  ^  Pin 6  ^  Pin 8  ^  Pin 10  ^  Pin 12  ^  Pin 14  ^  Pin 16  ^
-|  A17  |  A19  |  A21  |  A23  |  A25  |  0  |  0  |  1  |
-|< 100% 10em >|
-^  Pin 1  ^  Pin 3  ^  Pin 5  ^  Pin 7  ^  Pin 9  ^  Pin 11  ^  Pin 13  ^  Pin 15  ^
-|  A16  |  A18  |  A20  |  A22  |  A24  |  0  |  1  |  0  |
-== P2 ==
-|< 100% 10em >|
-^  Pin 2  ^  Pin 4  ^  Pin 6  ^  Pin 8  ^  Pin 10  ^  Pin 12  ^  Pin 14  ^  Pin 16  ^
-|  A1  |  A3  |  A5  |  A7  |  A9  |  A11  |  A13  |  A15  |
-|< 100% 10em >|
-^  Pin 1  ^  Pin 3  ^  Pin 5  ^  Pin 7  ^  Pin 9  ^  Pin 11  ^  Pin 13  ^  Pin 15  ^
-|  A0  |  A2  |  A4  |  A6  |  A8  |  A10  |  A12  |  A14  |
-== P3 ==
-|< 100% 10em >|
-^  Pin 2  ^  Pin 4  ^  Pin 6  ^  Pin 8  ^  Pin 10  ^  Pin 12  ^  Pin 14  ^  Pin 16  ^
-|  D1  |  D3  |  D5  |  D7  |  D9  |  D11  |  D13  |  D15  |
-|< 100% 10em >|
-^  Pin 1  ^  Pin 3  ^  Pin 5  ^  Pin 7  ^  Pin 9  ^  Pin 11  ^  Pin 13  ^  Pin 15  ^
-|  D0  |  D2  |  D4  |  D6  |  D8  |  D10  |  D12  |  D14  |
-== P4 ==
-|< 100% 10em >|
-^  Pin 2  ^  Pin 4  ^  Pin 6  ^  Pin 8  ^  Pin 10  ^  Pin 12  ^  Pin 14  ^  Pin 16  ^
-|  NE2  |  NE4  |  NWE  |  NBU  |  1  |  1  |  1  |  CLK  |
-|< 100% 10em >|
-^  Pin 1  ^  Pin 3  ^  Pin 5  ^  Pin 7  ^  Pin 9  ^  Pin 11  ^  Pin 13  ^  Pin 15  ^
-|  NE1  |  NE3  |  NOE  |  NBL  |  1  |  1  |  1  |  NRST  |
-==== Visualization on Oscilloskope ====
-For educational purpouse there is a mode to visualize the bus on a oscilloskope. \\
-The ports are specially configured to directly plug in the logic probe of a Tektronix logic analyzer. \\ \\
-> {{ctboard_mode_3.svg?48px }} This functionality is independent of the CT Board mode.
-> Supported modes: **3**.
-\\ {{ ctboard_gpio_probe.svg?400em }} \\ \\
-=== Pin Out ===
-== P1 ==
-|< 100% 10em >|
-^  Pin 2  ^  Pin 4  ^  Pin 6  ^  Pin 8  ^  Pin 10  ^  Pin 12  ^  Pin 14  ^  Pin 16  ^
-|  GND  ||||||||
-|< 100% 10em >|
-^  Pin 1  ^  Pin 3  ^  Pin 5  ^  Pin 7  ^  Pin 9  ^  Pin 11  ^  Pin 13  ^  Pin 15  ^
-|  D15  |  D14  |  D13  |  D12  |  D11  |  D10  |  D9  |  D8  |
-== P2 ==
-|< 100% 10em >|
-^  Pin 2  ^  Pin 4  ^  Pin 6  ^  Pin 8  ^  Pin 10  ^  Pin 12  ^  Pin 14  ^  Pin 16  ^
-|  GND  ||||||||
-|< 100% 10em >|
-^  Pin 1  ^  Pin 3  ^  Pin 5  ^  Pin 7  ^  Pin 9  ^  Pin 11  ^  Pin 13  ^  Pin 15  ^
-|  D7  |  D6  |  D5  |  D4  |  D3  |  D2  |  D1  |  D0  |
-== P3 ==
-|< 100% 10em >|
-^  Pin 2  ^  Pin 4  ^  Pin 6  ^  Pin 8  ^  Pin 10  ^  Pin 12  ^  Pin 14  ^  Pin 16  ^
-|  GND  ||||||||
-|< 100% 10em >|
-^  Pin 1  ^  Pin 3  ^  Pin 5  ^  Pin 7  ^  Pin 9  ^  Pin 11  ^  Pin 13  ^  Pin 15  ^
-|  A7  |  A6  |  A5  |  A4  |  A3  |  A2  |  A1  |  A0  |
-== P4 ==
-|< 100% 10em >|
-^  Pin 2  ^  Pin 4  ^  Pin 6  ^  Pin 8  ^  Pin 10  ^  Pin 12  ^  Pin 14  ^  Pin 16  ^
-|  GND  ||||||||
-|< 100% 10em >|
-^  Pin 1  ^  Pin 3  ^  Pin 5  ^  Pin 7  ^  Pin 9  ^  Pin 11  ^  Pin 13  ^  Pin 15  ^
-|  A10  |  A9  |  A8  |  NOE  |  NWE  |  NBL  |  NBU  |  CLK  |